The present invention relates to a semiconductor memory, and more specifically to a method for relieving a defective memory cell and a semiconductor memory incorporating therein a circuit for relieving a defective memory cell.
In a process for fabricating a semiconductor memory, defective memory cells occur often, and if the defective memory cells are fount out in an inspecting step, even if only one bit is defective, the whole of the memory chip is rejected. Therefore, particularly, in a semiconductor memory having a large memory capacity, redundant memory cells are previously provided to relieve the defective cells. In order to relieve the defective cells, it is necessary to provide on a chip a non-volatile memory for storing information for substituting a nondefective redundant memory cell for the defective memory cell found out in a chip test time.
In the prior art, in many cases, a memory of the information for substituting the nondefective redundant memory cell for the defective memory cell, is realized by a fuse (whether or not the fuse is broken) provided in the semiconductor memory.
Alternatively, a relief circuit has been proposed which uses a ferroelectric capacitor in place of the fuse. The relief circuit using a ferroelectric capacitor is disclosed by for example JP-A-2000-215687 or JP-A-09-128991.
Now, the redundant relief circuit disclosed in JP-A-09-128991 will be described with reference to FIGS. 22 and 23. In FIG. 22, an address signal supplied from an external of the chip is inputted to a row decoder 2205 and a column decoder 2202, and then, supplied to defective memory cell relief circuits 2206 and 2203. When a memory cell designated by the given address is a defective memory cell, an address translation is carried out by the defective memory cell relief circuits 2206 and 2203, so that a nondefective redundant memory cell is accessed.
FIG. 23 illustrates the defective memory cell relief circuit. In FIG. 23, a relief address storing circuit 2302 is constituted of xe2x80x9cn+1xe2x80x9d ferroelectric memory cells. The ferroelectric memory cell FE is constituted of one nMOS transistor and one ferroelectric capacitor. The relief address storing circuit 2302 stores an address of xe2x80x9cnxe2x80x9d bits and information of one bit indicative of substitution or nonsubstitution. A relief address writing circuit 2301 is used for writing a substitution information into the relief address storing circuit 2302.
A relief address reading circuit 2303 reads the substitution information from the relief address storing circuit 2302 and supplies the read-out substitution information into a redundant decoder 2310.
The redundant decoder 2310 compares the read-out substitution information with the address inputted to the chip. When coincidence is obtained, namely, when the address is replaced by another, the redundant decoder 2310 selects a redundant memory cell. On the other hand, when coincidence is not obtained, the redundant decoder 2310 allows a memory cell designated by the inputted address to be selected.
The redundant relief circuit disclosed in the above referred JP-A-09-128991 can reduce the number of steps in the test time, in comparison with the prior art relief address storing circuit using the fuse, since a trimmer or the like is not used, and since an electrical writing is possible. In addition, the redundant relief circuit disclosed in JP-A-09-128991 can reduce an occupying area for the whole of the relief circuit.
On the other hand, the above referred JP-A-2000-215687 discloses a memory device having a defective memory cell relief circuit in particular for a ferroelectric memory (FeRAM), in which a redundant file memory for storing the substitution information indicative of whether or not it is a defective cell to be replaced by a redundant cell, is constituted of memory cells having the same arrangement as that of main memory cells, and the redundant file memory is accessed as the same time as the main memory cells are accessed, so that a substitution information stored in the redundant file memory is read out when the main memory cells are accessed, and the defective memory cell is replaced by the redundant cell in accordance with the substitution information.
This memory device will be described with reference to FIG. 24. In FIG. 24, each of columns COL0 to COL7 and RCOL is constituted to have 8 bit line pairs. Substitution is carried out in units of column. The substitution information is stored in ferroelectric memory cells, which are located in the same word lines as those of the main memory cells.
The substitution information is read out as the same time as the main memory cells are accessed. The read-out substitution information is compared with the column address inputted, and when coincidence is obtained, redundant memory cells (of 8 bits since it is in units of column) is selected.
Since the substitution information storing cells are arranged in the same manner as that of the main memory cells, a writing/reading circuit can be shared with the main memory cells, so that a construction can be simplified. In addition, since the writing/reading operation of the main memory cells is the same as that of the substitution information storing cells, the testing becomes easy, and it is possible to write the substitution information after packaged. Furthermore, since the substitution information storing cells are arranged in the same word lines as those of the main memory cells, it is possible to set the substitution information of the defective memory cells in units of word line, and therefore, the degree of substitution is very high.
Incidentally, JP-A-2000-067594 discloses a non-volatile semiconductor memory device having a latch circuit latching, at a power-on time, an address data of a defective address storing part which stores an address of a defective memory cell.
However, the arrangement disclosed in the above referred JP-A-09-128991 so configured to store the substitution information by action of the ferroelectric memory cells is disadvantageous in that the whole of the relief circuit needs a large area and the access time becomes long. In other words, since the fuses are replaced with the ferroelectric memory cells, the area for the fuses becomes greatly reduced. However, a dedicated writing/reading circuit becomes necessary, and further, it is necessary to provide on the chip a pad or pads for supplying data to written. The overhead of the chip area attributable to the installation of the relief circuit cannot become so small.
In addition, in order to replace the defective memory cell, the address inputted to the chip is supplied to the defective memory relief circuit once, so that the address comparison is carried out within the defective memory relief circuit, and then, if the inputted address is to be replaced, the address translation is carried out, and thereafter, a redundant memory cell is selected finally. Therefore, the access time becomes long.
On the other hand, the memory device disclosed in the above referred JP-A-2000-215687 is also disadvantageous in the chip area and in the access time. In addition, it has another problem in which the characteristics of the ferroelectric capacitor is deteriorated. Namely, in this prior art construction, the substitution information storing cells are located in the same array and in the same word lines as those of the main memory cells, and the substitution information stores the column address of the defective memory cells. In the case that the memory cell array is constituted of 8 columns (8 bit line pairsxc3x978 columns=64 bit line pairs), the redundant memory cells are organized in one column (8 bits), and therefore, at least three bits are required to indicate the column address, and a bit indicative of substitution or nonsubstitution is required, so that at least four bits are required in total. Accordingly, only in the memory cell array excluding a peripheral circuit for the substitution, the area overhead reaches 18% or more. Namely, the area overhead attributable to the installation of the redundant circuit is very large.
Furthermore, since the substitution information storing cells are located in the same word lines as those of the main memory cells, the substitution has not yet been achieved at the moment a signal voltage read out from the memory cell has been amplified by a sense amplifier. The read-out column address is decoded, and compared with the given column address, and thereafter, the substitution operation is carried out, so that a column selection signal (S0 to SR) is generated. Comparing with the case in which the substitution is not carried out, an overhead is inevitably generated in the access time. In addition, since the substitution information is read out in every memory access, the deterioration in characteristics of the ferroelectric capacitors is unavoidable. Namely, there is possibility that an erroneous substitution occurs because of the deterioration in characteristics of the substitution information storing cells.
Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor memory which has minimized the area overhead and the access time overhead attributable to the installation of the defective memory cell relief circuit, whereby a semiconductor memory having an elevated chip yield of production and an increased reliability can be obtained.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor memory including a memory cell array constituted of a number of memory cells arranged in the form of a matrix having a number of rows and a number of columns, and a defective memory cell relief means, wherein the memory cell array includes main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, and the defective memory cell relief means includes a means for operating, in place of a column including a defective memory cell, a non-defective column adjacent to the column including the defective memory cell.
Specifically, the defective memory cell relief means includes a means for inhibiting access to the column including the defective memory cell in accordance with the content of the substitution information storing memory cells, a means for operating, in place of the column including a defective memory cell within the main memory cells, a non-defective column within the main memory cells, adjacent to the column including the defective memory cell, and a means for compensating shortage in the main memory cells with the redundant memory cells.
More specifically, the defective memory cell relief means includes a control circuit for generating a control signal on the basis of the content of the substitution information storing memory cells.
The defective memory cell relief means preferably further includes a Y selection circuit receiving a Y selection signal and the control signal for selecting one column of the columns in the memory cell array to connect a bit line of the selected column to an input/output line.
Alternatively, the control circuit includes at least xe2x80x9cnxe2x80x9d bits of volatile memory cells for storing the substitution information of xe2x80x9cnxe2x80x9d bits stored in one row of substitution information storing memory cells.
The control circuit can further include a decoder receiving the substitution information stored in the at least xe2x80x9cnxe2x80x9d bits of volatile memory cells, for generating the control signal.
According to anther aspect of the present invention, there is provided a semiconductor memory including first and second memory cell arrays each constituted of a number of memory cells arranged in the form of a matrix having a number of rows and a number of columns, and a defective memory cell relief means, wherein each of the first and second memory cell arrays includes main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, the substitution information for the first memory cell array being stored in the substitution information storing memory cells in the second memory cell array, the substitution information for the second memory cell array being stored in the substitution information storing memory cells in the first memory cell array, so that when the first memory cell array is accessed, substitution information is simultaneously read out from the substitution information storing memory cells in the second memory cell array in order to relieve a defective memory cell within the first memory cell array.
According to still anther aspect of the present invention, there is provided a semiconductor memory including a memory cell array constituted of a number of memory cells arranged in the form of a matrix having a number of rows and a number of columns, and a defective memory cell relief means, wherein the memory cell array includes main memory cells arranged in the form of a matrix having a number of rows and a number of columns and at least one column of redundant memory cells, and the defective memory cell relief means includes at least xe2x80x9cnxe2x80x9d bits of ferroelectric non-volatile memory cells, for storing substitution information of xe2x80x9cnxe2x80x9d bits.
In one embodiment of the semiconductor memory, each of the at least xe2x80x9cnxe2x80x9d bits of ferroelectric non-volatile memory cells comprises two ferroelectric capacitors and at least four transistors.
For example, only the substitution information storing memory cells are a non-volatile memory cell, or alternatively, the main memory cells, the redundant memory cells and the substitution information storing memory cells are a non-volatile memory cell, or specifically, a ferroelectric non-volatile memory cell.
According to a further aspect of the present invention, there is provided a semiconductor memory comprising
a memory cell array including main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, the substitution information storing memory cells being constituted of a rewritable non-volatile memory cell;
a Y selection circuit associated with the memory cell array and receiving a Y selection signal to connect an input/output line to a bit line of the column designated by the Y selection signal;
a control circuit for generating a control signal in response to substitution information which is read out from the substitution information storing memory cells just after a power supply is turned on for the semiconductor memory (namely, an ordinary reading/writing operation) and which indicates that a column including a defective memory cell should be replaced with another column having no defective memory cell, the control signal being supplied to the Y selection circuit for inhibiting access to the column including the defective memory cell and for replacing the column including the defective memory cell by one column of the other columns and the at least one column of redundant memory cells.
In one embodiment of the semiconductor memory, each of the at least one row of substitution information storing memory cells is constituted of for example a ferroelectric memory cell (FeRAM), which for example comprises a pair of ferroelectric capacitors each having one end connected to a plate line, and a pair of cell transistors connected between a pair of complementary bit lines and the other end of the pair of ferroelectric capacitors, respectively, a gate of each of the pair of cell transistors being connected to a word line. In this connection, each of the main memory cells can be formed of a ferroelectric memory cell.
With the above mentioned arrangement, since the at least one row of substitution information storing memory cells are added to the main memory cells arranged in the form of a matrix having a number of rows and a number of columns, and since only the one row of substitution information storing memory cells store the substitution information, the area overhead of the memory cell array is minimized. In addition, since the substitution information is read out from the substitution information storing memory cells only one time just after a power supply is turned on for the semiconductor memory, it is possible to avoid the characteristics deterioration of the substitution information storing memory cells which may be formed of the ferroelectric memory cell.
Furthermore, since the substitution of the defective memory cell (namely, the column including the defective memory cell) is completed before the Y selection signal (column selection signal) is supplied to the Y selection circuit, no overhead occurs in the access time.
Therefore, the present invention provides a highly reliable semiconductor memory device having a minimized area overhead and no access time overhead.
Specifically, the Y selection circuit receiving the Y selection signal and the control signal, is so configured that when the column designated by the Y selection signal is the column including the defective memory cell, the Y selection circuit selects a column adjacent to the column designated by the Y selection signal, and connects the input/output line to a bit line of the selected column adjacent to the column designated by the Y selection signal.
In one embodiment of the semiconductor memory, the Y selection circuit is controlled by the control signal to select the column designated by the Y selection signal, until a column just before the column including the defective memory cell, and to select, a column adjacent to the column designated by the Y selection signal for the column designated by the Y selection signal and succeeding columns.
In a specific embodiment of the semiconductor memory, the memory cell array includes (0)th to (j)th columns of main memory cells and a (j+1)th column of redundant memory cells, and the Y selection circuit includes:
a first series circuit composed of a first Y switch and a first control switch connected in series between the input/output line and a bit line of a (k)th column (k=1 to (j+1)) excluding the (0)th column, the first Y switch being on-off controlled by a Y selection signal corresponding to a (kxe2x88x921)th column, and the first control switch being on-off controlled by a control signal CS(kxe2x88x921) generated from the data read out from the substitution information storing memory cell corresponding to the (kxe2x88x921)th column, and
a second series circuit composed of a second Y switch and a second control switch connected in series between the input/output line and a bit line of a (kxe2x88x921)th column excluding the (j+1)th column, the second Y switch being on-off controlled by the Y selection signal corresponding to the (kxe2x88x921)th column, and the second control switch being on-off controlled by an inverted signal of the control signal CS(kxe2x88x921) generated from the data read out from the substitution information storing memory cell corresponding to the (kxe2x88x921)th column.
The substitution information storing memory cells are read and written by use of a writing/reading circuit for the main memory cells
Each of the substitution information storing memory cells includes a ferroelectric capacitor having one end connected to a plate line and a cell transistor connected between a bit line and the other end of the ferroelectric capacitor, the cell transistor having a gate connected to a word line.
Each of the main memory cells includes a ferroelectric capacitor having one end connected to a plate line and a cell transistor connected between a bit line and the other end of the ferroelectric capacitor, the cell transistor having a gate connected to a word line.
The control circuit includes a memory circuit for receiving and holding the substitution information read out from the one row of substitution information storing memory cells, and the control circuit generates the control signal on the basis of the substitution information held in the memory circuit.
Specifically, in response to one Y selection signal, a plurality of bit lines are simultaneously selected and connected to a plurality of input/output lines, and when the selected plurality of bit lines includes a bit line connected to the column including the defective memory cell, the a bit line connected to the column including the defective memory cell is not selected, and a bit line of a column adjacent to the column including the defective memory cell is selected.
Alternatively, the substitution information includes a plurality of bits indicative of an address of one column within the memory cell array excluding the column of redundant memory cells, and an information bit indicative of substitution or non-substitution, and word lines of the memory cell array excluding the row of substitution information storing memory cells are divided into a plurality of groups of word lines, and one substitution information is allocated to each one group of word lines, so that a substitution column can be different from one group of word lines to another group of word lines, whereby even if a plurality of defective memory cells exist in different columns, the defective memory cells can be relieved.
For example, the control circuit selects substitution information for a group of word lines to be accessed, from the substitution information read out from the one row of substitution information storing memory cells excluding the column of redundant memory cells, and the control circuit generates the control signal on the basis of the selected substitution information.
Furthermore, substitution information for a group of word lines to be accessed is selected on the basis of a signal obtained by decoding a bit or bits identifying the plurality of groups of word lines, of an X address, and the selected substitution information is supplied to a decode circuit, which generates the control signal to the Y selection circuit.
In addition, the control circuit includes memory cells of the number corresponding to the number of columns in the memory cell array excluding the column of redundant memory cells, each of the memory cells storing the data read out from a corresponding memory cell of the row of substitution information storing memory cells, and
the substitution information for a group of word lines to be accessed is selected from the substitution information stored in the memory cells of the control circuit, on the basis of a signal obtained by decoding a bit or bits identifying the plurality of groups of word lines, of an X address, and the selected substitution information is supplied to the decode circuit.
According to a further aspect of the present invention, there is provided a semiconductor memory comprising a memory cell array divided into a plurality of sub-arrays coupled through a local bus, each of the sub-arrays including a number of main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, each of the sub-arrays being associated with a Y selection circuit and a plurality of sense amplifiers each provided for a bit line of one corresponding column,
wherein in the bit line of each column, a transfer gate is inserted between the substitution information storing memory cells and the main memory cells and the redundant memory cells, and is controlled by a separation control signal to separate the main memory cells and the redundant memory cells from the associated sense amplifiers and the substitution information storing memory cells,
wherein a pair of the sub-arrays are mated so that the substitution information storing memory cells in each of the pair of sub-arrays store substitution information for the other of the pair of sub-arrays, and when one of the pair of sub-arrays is read out, the substitution information for the one of the pair of sub-arrays is read out from the substitution information storing memory cells in the other of the pair of sub-arrays while separating the main memory cells and the redundant memory cells in the other of the pair of sub-arrays from the associated sense amplifiers and the substitution information storing memory cells in the other of the pair of sub-arrays by turning off the transfer gates in the other of the pair of sub-arrays, and the read-out substitution information is transferred through the local bus, as a control signal, to the Y selection circuit associated with the one of the pair of sub-arrays,
so that the Y selection circuit associated with the one of the pair of sub-arrays receives a Y selection signal and the control signal, to connect the bit line of the column designated by the Y selection signal to an input/output line when the control signal indicates that the column designated by the Y selection signal is not a column including a defective memory cell, and to connect the input/output line to a column adjacent to the column designated by the Y selection signal when the control signal indicates that the column designated by the Y selection signal is a column including a defective memory cell.
Specifically, word lines of each sub-array excluding the row of substitution information storing memory cells are divided into-a plurality of groups of word lines, and one substitution information is allocated to one group of word lines, so that a substitution column can be different from one group of word lines to another group of word lines, whereby even if a plurality of defective memory cells exist in different columns, the defective memory cells can be relieved. And, the semiconductor memory includes a selection circuit for selecting substitution information for a group of word lines to be accessed, on the basis of a signal obtained by decoding a bit or bits identifying the plurality of groups of word lines, of an X address, and a decode circuit receiving the selected substitution information for generating the control signal which is supplied through the local bus to the Y selection circuit of the other sub-array.
According to a further aspect of the present invention, there is provided a semiconductor memory comprising:
a memory cell array including a number of main memory cells arranged in the form of a matrix having a number of rows and a number of columns and at least one column of redundant memory cells;
a plurality of sense amplifiers each provided for a bit line of one corresponding column in the memory cell array;
a Y selection circuit associated with the memory cell array;
a control circuit including a plurality of substitution information storing memory cells for generating, on the basis of substitution information read out from the substitution information storing memory cells, a control signal to the Y selection circuit for inhibiting access to a column including a defective memory cell and for replacing the column including the defective memory cell by one column of the other columns and the at least one column of redundant memory cells,
wherein when a power supply is turned on, the substitution information is read out from the substitution information storing memory cells, and the Y selection circuit receiving a Y selection signal and the control signal, connects the bit line of the column designated by the Y selection signal to an input/output line when the control signal indicates that the column designated by the Y selection signal is not a column including a defective memory cell, and to connect the input/output line to a column including no defective memory cell when the control signal indicates that the column designated by the Y selection signal is a column including a defective memory cell.
Each of the substitution information storing memory cells included in the control circuit can be formed of a ferroelectric memory cell, or alternatively, another type of non-volatile memory cells such as a EEPROM cell, a flash memory cell or a MRAM (magnetic random access memory) cell.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.